1. Field of the Invention
The present invention relates generally to a metal-oxide semiconductor (MOS) transistor and related methods of manufacture. More particularly, the present invention relates to a MOS transistor including a multi-work function metal nitride gate electrode, a complementary metal-oxide semiconductor (CMOS) integrated circuit device including the same, and related methods of manufacture.
A claim of priority is made to Korean Patent Application No. 10-2005-0036416, filed on Apr. 29, 2005, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
Modern semiconductor devices typically include large numbers of active devices such as MOS transistors. As the level of integration in the semiconductor devices increases, the size of the MOS transistors tends to decrease accordingly. As a result, the channel length of MOS transistors tends to be reduced. Unfortunately, as the channel length of MOS transistors decreases, the MOS transistors become increasingly susceptible to the short channel effect, which can significantly impair the performance of the semiconductor devices.
In order to suppress the short channel effect, a halo ion implantation technique is commonly used. In the halo ion implantation technique, impurity ions having the same conductivity type as a channel region of the MOS transistor are implanted into opposing edges of the channel region below a gate electrode of the MOS transistor using a tilted ion implantation process. As a result, the impurity concentration in the opposing edges of the channel region increases to prevent the threshold voltage of the MOS transistor from abruptly decreasing due to the short-channel effect. Unfortunately, where the halo ion implantation technique is used to fabricate short channel MOS transistors, current drivability of the short channel MOS transistors may be degraded. This is because the halo ion implantation technique leads to an increase in the impurity concentration of opposing edges of the channel region. Accordingly, in order to address the problem created by the halo ion implantation technique, a gate electrode including at least two conductive layers having work functions different from each other is used in high-performance short channel MOS transistors.
A MOS transistor employing the multi-work function gate electrode and a method of manufacturing the same are disclosed, for example, in U.S. Pat. No. 6,586,808 B1 to Xiang et al. (hereafter, Xiang). According to Xiang, a source region and a drain region are formed in a semiconductor layer and a gate electrode is formed on a channel region between the source region and drain regions. The gate electrode includes a pair of side gate electrodes adjacent to the source and drain regions and a central gate electrode between the side gate electrodes. The side gate electrodes are formed of a material layer having a work function different from that of the central gate electrode. For example, the central gate electrode is typically formed of any one of a silicon layer, a silicon-germanium (Si—Ge) layer, a metal layer and a metal compound layer, and the side gate electrodes are also typically formed of any one of a silicon layer, a silicon-germanium (Si—Ge) layer, a metal layer and a metal compound layer.
In Xiang, two separated anisotropic etching steps are required in order to form the side gate electrodes and gate spacers on outer sidewalls of the side gate electrodes. The an isotropic etching steps may cause severe etching damage to the channel region, thereby degrading a junction leakage current characteristic of the source and drain regions. Furthermore, it is difficult to form high-performance CMOS integrated circuit devices including an N conductivity type, metal-oxide semiconductor (NMOS) or a P conductivity type, metal-oxide semiconductor (PMOS) transistors using the techniques disclosed in Xiang. This is because Xiang requires complicated processes to form side gate electrodes with two different material layers for the NMOS and PMOS transistors.
Another method of manufacturing a MOS transistor having a multi-work function gate electrode is disclosed, for example, in U.S. Pat. No. 6,528,399 B1 to Alieu et al. (hereafter, Alieu). According to Alieu, an initial gate electrode comprising a silicon layer or a silicon layer containing a small amount of germanium is formed on a semiconductor substrate. An outer germanium layer is formed on at least the sidewalls of the initial gate electrode, and the substrate having the outer germanium layer is annealed to diffuse germanium atoms of the outer germanium layer into edges of the initial gate electrode. As a result, a central gate electrode composed of a silicon layer and side gate electrodes including a silicon germanium layer are formed.
The silicon germanium gate electrodes (e.g., the side gate electrodes) have a work function lower than that of the silicon gate electrode (e.g., the central gate electrode). Therefore, the gate electrode according to Alieu can suppress the short channel effect in PMOS transistors. Unfortunately, however, it may be difficult to apply the gate electrode of Alieu to NMOS transistors.